ThothII

T

marcopan 0dcc0246dc docs(plan): tht porting CLI + skill — implementation plan

Piano da spec 2026-06-27-cli-port-completo-skill-riscritta-design.md.
Struttura in onde: -1 (renaming tht isolato), 0 (backend), 0b (evidence+LSH setup),
1 (radici CLI + phase drift), 2 (vector), 3 (foglia + metadata memory), 4 (SQL/CTE),
S (skill riscritta), L2 (sessione manuale).

TDD per logica nuova (schema_linking_phase, require_phase_or_exit, arricchimento
metadata memory); port+smoke+commit per i port verbatim (logica gia' validata in
ChironeWp3). pytest verde (109 passed) a ogni task come gate di regressione.

Self-review: copertura spec completa (11 decisioni), nessun placeholder, type
consistency verificata. Gap residui onesti: circularita' session_cmd<->sql_cmd
(risolto con import lazy), RPC server mancanti (fuori piano codice), L2 manuale.

2026-06-27 10:13:44 +02:00

.kilo

chore: init ThothII repo — gitignore references, baseline docs (PRD, spec, harness plan)

2026-06-26 22:00:43 +02:00

docs/superpowers

docs(plan): tht porting CLI + skill — implementation plan

2026-06-27 10:13:44 +02:00

harness

fix(harness): workspace + write-URL + L2 tests per accesso REST reale

2026-06-27 08:20:36 +02:00

prd

chore: init ThothII repo — gitignore references, baseline docs (PRD, spec, harness plan)

2026-06-26 22:00:43 +02:00

.gitignore

chore: init ThothII repo — gitignore references, baseline docs (PRD, spec, harness plan)

2026-06-26 22:00:43 +02:00